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lvds interface ics 35bit lvds receiver 5:35 deserializer BU8255KVT description lvds interface ic of rohm "serializer" "deserialize r" operate from 8mhz to 150mhz wide clock range, and number of bits range is from 35 to 70. data is transm itted seven times (7x) stream and reduce cable number by 3(1/3) or less. the rohm's lvds has low swing mode to be able to expect further low emi. features five channels of lvds data strea m are converted to 35bits data of parallel lvcmos level outputs. 30bits of rgb output data, 5bits of timing and control output data(hsync, vsync, de, ctl1 and ctl2) are transmitted available. support clock frequency from 8mhz up to 112mhz. support consumer video format including 480i, 480p, 720p and 1 080i as well. support many kinds of pc video formats such as vga, svga, xga and sxga. provide 784mbps per 1ch or 3.92gbps per device throughput rate using 112mhz clock rate. user programmable lvcmos data o utput triggering timing by usin g either rising or fa lling edge of clock. 30bit lvds transmitter is r ecommended to use bu8254kvt. applications flat panel display precaution ?this chip is not designed to protect from radioactivity. ?the chip is made strictly for the specific application or e quipment. then it is necessary that the unit is measured as need. ?this document may be used as strategic t echnical data which subjects to cocom regulations. status of this document the japanese version of this document is the formal specificati on. a customer may use this translation version only for a referenc e to help reading the formal version. if there are any differences in translation version of this doc ument, formal version takes priority. jun.2008
2 / 17 block diagram figure-1 block diagram lvcmos output sampling clocks pll rclk / (8112mhz) clkout ra / reserve pd oe r/f lvds differential input ra6-ra0 7 rb / rb6-rb0 7 rc / rc6-rc0 7 rd / rd6-rd0 7 re / re6-re0 7 7 serial to parallel lvcmos input serial to parallel serial to parallel serial to parallel serial to parallel
3 / 17 tqfp64v package specification figureC2 tqfp64v package BU8255KVT lot no. product no. 1pin mark
4 / 17 pin diagram figure-3 pin diagram (top view) vdd ra1 ra0 ra2 gnd ra3 ra4 ra5 ra6 rb0 rb1 vdd rb2 rb3 rb4 rb5 rb6 clkout gnd rc0 rc1 rc2 rc3 rc4 rc5 vdd rc6 rd0 rd1 rd2 rd3 rd4 gnd reserve pd oe r/f re6 re5 re4 vdd re2 re1 re0 rd6 rd5 gnd ra_ pvdd 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 64-pin tqfp (top view) ra+ rb_ rb+ pgnd rd_ rd+ re_ re+ lgnd rclk+ rclk_ rc_ rc+ lvdd re3
5 / 17 pin description table .1: pin description pin name pin no. i/o description ra+, ra- 50,49 lvds input lvds data input + : positive input of lvds data differential pair. - : negative input of lvds data differential pair. rb+, rb- 52,51 lvds input rc+, rc- 55,54 lvds input rd+, rd- 60,59 lvds input re+, re- 62,61 lvds input rclk+, rclk- 57,56 lvds input lvds clock input ra6ra0 40,41,42,43, 45,46,47 output lvcmos data outputs. rb6rb0 32,33,34,35, 36,38,39 output rc6rc0 22,24,25,26, 27,28,29 output rd6rd0 14,15,17,18, 19,20,21 output re6re0 6,7,8,10,11,1 2,13 output reserve 2 input reserved input, must be low for normal operat ion. pd 3 input power down input for t he internal system. h: normal operation. l: power down (all ou tput are low). oe 4 input power down input for the data output driver. h: output enable (normal operation). l: output disable(all outputs are hi-z). r/f 5 input select input pin for data out put clock triggering edge. h: output data is latched on rising edge. l: output data is latched on falling edge. vdd 9,23,37,48 power 3.3v output driver and digital core power supply pin. clkout 31 output lvcmos level clock output. gnd 1,16,30,44 ground gnd pin for both data output driver cells and the digital cores. lvdd 53 power power supply pin for lvds inputs. lgnd 58 ground ground pin for lvds inputs. pvdd 64 power power su pply pin for pll core. pgnd 63 ground ground pin for pll core.
6 / 17 function description table .2: function explanation list pd r/f oe data output (rxn) *1 clock output 0 0 0 hi-z hi-z 0 0 1 all fixed low fixed low 0 1 0 hi-z hi-z 0 1 1 all fixed low fixed low 1 0 0 hi-z hi-z 1 0 1 data output output data is latched by falling edge of clock. 1 1 0 hi-z hi-z 1 1 1 data output output data is latched by rising edge of cloc k *1rxn x = a,b,c,d,e n = 0,1,2,3,4,5,6
7 / 17 electrical characteristics rating table .3: absolute maximum rating item symbol value unit min. max. supply voltage v dd -0.3 4.0 v input voltage v in -0.3 v dd +0.3 v output voltage v out -0.3 v dd +0.3 v storage temperature range tstg -55 125 table .4: package power package pd(mw) derating(mw/) *1 tqfp64v 700 7.0 1000 *2 10.0 *2 *1 at temperature ta > 25 *2 package power when mounting on the pcb board. the size of pcb board :70701.6mm 3 the material of pcb board :the fr 4 glass epoxy board.(3% or les s copper foil area) table .5: recommended operating conditions item symbol value unit condition min. typ. max. supply voltage v dd 3.0 3.3 3.6 v vdd, lvdd, pvdd supply noise voltage v noz - - 0.1 v operating temperature range topr -20 - 85 clock frequency from 8mhz up to 90mhz 0 - 70 clock frequency from 90mhz up to 112mhz
8 / 17 dc characteristics table .6: lvcmos dc character v dd =3.0v3.6v, ta=-2085 symbol item value unit condition min. typ. max. v ih high input voltage v dd 0.8 - v dd v v il low input voltage 0.0 - v dd 0.2 v v oh high output voltage v dd -0.5 - v dd v i oh =-4ma (data) i oh =-8ma (clock) v ol low output voltage 0.0 - 0.4 v i ol =4ma (data) i ol =8ma (clock) i inc input current - - 10 a 0v v in v dd table .7: lvds recei ver dc character v dd =3.0v3.6v, ta=-20 85 symbol item value unit condition min. typ. max. v th differential input high threshold - - 100 mv v oc *1 =1.2v v tl differential input low threshold -100 - - mv v oc *1 =1.2v i inl input current - - 25 a v in =2.4v / 0v v dd =3.6v *1 common mode voltage
9 / 17 supply current table .8: supply current symbol item value unit condition min. max. i rccg receiver supply current (gray scale pattern) 52 - ma fclkout=90mhz c l =8pf, v dd =3.3v i rccw receiver supply current (worst case pattern) 95 - ma fclkout=90mhz c l =8pf, v dd =3.3v i rccs receiver power down supply current - 10 a pd=l, oe=l gray scale pattern worst case pattern (maximum power condition) clkout rx0 rx1 rx2 rx3 rx4 rx5 rx6 x=a,b,c,d,e clkout rx0 rx2 rx3 rx4 rx5 rx6 rx figure-4 gray scale pattern figure-5 worst case pattern x=a,b,c,d,e
10 / 17 ac characteristics table .9 : switching characteristics symbol item value unit min. typ. max. t rcp clkout period 8.93 - 125 ns t rch clkout "h" time - 0.5t rcp -1.0 - ns t rcl clkout "l" time - 0.5t rcp -1.0 - ns t rs lvcmos data setup to clkout 0.5t rcp -1.4 - - ns t rh lvcmos data hold from clkout 0.23t rcp -1.0 - - ns t tlh lvcmos data rise time - 1.0 2.0 ns t thl lvcmos data fall time - 1.0 2.0 ns t rip1 input data position0 -0.25 0.0 +0.25 ns t rip0 input data position1 7 t rcip -0.25 7 t rcip 7 t rcip +0.25 ns t rip6 input data position2 2 7 t rcip -0.25 2 7 t rcip 2 7 t rcip +0.25 ns t rip5 input data position3 3 7 t rcip -0.25 3 7 t rcip 3 7 t rcip +0.25 ns t rip4 input data position4 4 7 t rcip -0.25 4 7 t rcip 4 7 t rcip +0.25 ns t rip3 input data position5 5 7 t rcip -0.25 5 7 t rcip 5 7 t rcip +0.25 ns t rip2 input data position6 6 7 t rcip -0.25 6 7 t rcip 6 7 t rcip +0.25 ns t rpll phase locked loop set time - - 10.0 ms t rcip clock input period 8.93 - 125 ns
11 / 17 ac timing diagrams lvcmos phase-locked loop set time c l =8pf lvcmos output load lvcmos output 80% 20% 80% 20% t tlh t thl figureC6 lvcmos output timing figureC7 phase-locked loop set time 3.0v t rpll v dd rclk +/- clkout pd v dd /2 v dd /2 rxn v dd /2 v dd /2 v dd /2 v dd /2 t rcp t rch t rcl v dd /2 t rs t rh clkout v dd /2 r/f= h r/f=l x=a,b,c,d,e n=0,1,2,3,4,5,6
12 / 17 lvds data, clock input timing figure-8 lvds data and clock input timing next cycle previous cycle current cycle rclk + (differential) t rcip t rip1 t rip0 t rip6 t rip5 t rip4 t rip3 t rip2 v diff =0v v diff =0v ra+/- ra1 ra0 ra6 ra5 ra4 ra3 ra2 ra1 ra0 ra6 ra2 ra3 rb+/- rb1 rb0 rb6 rb5 rb4 rb3 rb2 rb1 rb0 rb6 rb2 rb3 rc+/- rc1 rc0 rc6 rc5 rc4 rc3 rc2 rc1 rc0 rc6 rc2 rc3 rd+/- rd1 rd0 rd6 rd5 rd4 rd3 rd2 rd1 rd0 rd6 rd2 rd3 re+/- re1 re0 re6 re5 re4 re3 re2 re1 re0 re6 re2 re3
13 / 17 lvds data, clock input a nd lvsmos output timing ra+ / - rclk+/- ra6 lvds input rb+ / - rc+/- rd+/- re+/- ra5 ra4 ra3 ra2 ra1 ra0 rb6 rb5 rb4 rb3 rb2 rb1 rb0 rc6 rc5 rc4 rc3 rc2 rc1 rc0 rd6 rd5 rd4 rd3 rd2 rd1 rd0 re6 re5 re4 re3 re2 re1 re0 re06 valid lvcmos output valid valid valid valid valid valid valid valid valid clkout ra06 clkout rb06 rc06 (r/f=l) (r/f=h) rd06 figure-9 lvds data, clock input and lvcmos output timing
14 / 17 about the power on reset power on reset is not mand atory for this device. the pd pin should be set to hi gh level when power on reset pro cedure is not used. however, power on reset procedure is strongly recommend for int ernal logic initialization by following two methods. the method of using cr circuit. the method of using external specific ic. it is recommend to do enough examination fo r target application . BU8255KVT pd v dd figure-11 power on reset by external a cr circuit figureC12 power on reset by specific ic schottky barrier diode v dd internal reset 2.2f pd pd 10k 220 v t + v dd v dd detection voltage v dd internal reset pd v t + be careful of temperature of the capacitor especially over and again. b characteristic ceramics and function polymer aluminum electrolysis are recommended. td is approximately equal to 20ms when the left rc coleus are a pplied. figure-10 terminal connection when power on reset is not used. b characteristic ceramics. pd v dd vout power on ic (open drain output) gnd 220k 0.1f v dd v dd
15 / 17 10 lvds level input & output example: bu8254kvt lvcmos level input/falling edge/lvds normal(350mv) swing output BU8255KVT lvcmos level output/falling edge 1 recommended parts f.bead blm18a-series murata manufacturing co. 2 :if rs pin is tied to v dd ,lvds swing is 350m v. if rs pin is tied to gnd ,lvds swing is 200m v. vdd gnd 0.1uf lvds vdd 0.01uf 0.1uf 0.01uf clkin v dd f.bead clkin bu8254kvt ta0 r4 ta1 r5 ta2 r6 ta3 r7 ta4 r8 ta5 r9 ta6 g4 tb0 g5 tb1 g6 tb2 g7 tb3 g8 tb4 g9 tb5 b4 tb6 b5 tc0 b6 tc1 b7 tc2 b8 tc3 b9 tc4 hsync tc5 vsync tc6 de td0 r2 td1 r3 td2 g2 td3 g3 td4 b2 td5 b3 td6 te0 r0 te1 r1 te2 g0 te3 g1 te4 b0 te5 b1 te6 xrst xrst v dd rs r/f *2 lvds gnd pll vdd pll gnd 0.1uf 0.01uf tan tap tbn tbp tcn tcp tclkn tclkp tdn tdp ten tep pcb(transmitter) pcb(receiver) 100 100 100 100 100 100 ra- ra+ rb- rb+ rc- rc+ rclk- rclk+ rd- rd+ re- re+ 100twist pair cable or pcb trace 0.1uf 0.01uf 0.1uf 0.01uf lvdd lgnd pvdd pgnd f.bead BU8255KVT vdd gnd 0.1uf 0.01uf v dd clkout r4 r5 r6 r7 r8 r9 g4 g5 g6 g7 g8 g9 b4 b5 b6 b7 b8 b9 hsync vsync de r2 r3 g2 g3 b2 b3 r0 r1 g0 g1 b0 b1 clkout ra0 ra1 ra2 ra3 ra4 ra5 ra6 rb0 rb1 rb2 rb3 rb4 rb5 rb6 rc0 rc1 rc2 rc3 rc4 rc5 rc6 rd0 rd1 rd2 rd3 rd4 rd5 rd6 re0 re1 re2 re3 re4 re5 re6 pd dk r/f open open pd oe oe 0.1uf *1 *1
16 / 17 10bit small swing input & lvcmos level output example: bu8254kvt lvcmos level input/falling edge/lvds normal(350mv) swing output BU8255KVT lvcmos level output/falling edge 3 recommended parts f.bead blm18a-series murata manufacturing co. 4 :rs pin acts as vref input pi n when input voltage is set to half of high level signal input. we recommend to locate by-pass condenser near the rs pin. example for lvttl(1.8v input):(r1,r2)=(15k,5.6k) rs pin. 15k v dd r1 r2 c1=0.1uf 5.6k vdd gnd 0.1uf lvds vdd 0.01uf 0.1uf 0.01uf clkin v dd f.bead clkin bu8254kvt ta0 r4 ta1 r5 ta2 r6 ta3 r7 ta4 r8 ta5 r9 ta6 g4 tb0 g5 tb1 g6 tb2 g7 tb3 g8 tb4 g9 tb5 b4 tb6 b5 tc0 b6 tc1 b7 tc2 b8 tc3 b9 tc4 hsync tc5 vsync tc6 de td0 r2 td1 r3 td2 g2 td3 g3 td4 b2 td5 b3 td6 te0 r0 te1 r1 te2 g0 te3 g1 te4 b0 te5 b1 te6 xrst xrst *4 rs r/f *4 lvds gnd pll vdd pll gnd 0.1uf 0.01uf tan tap tbn tbp tcn tcp tclkn tclkp tdn tdp ten tep pcb(transmitter) pcb(receiver) 100 100 100 100 100 100 ra- ra+ rb- rb+ rc- rc+ rclk- rclk+ rd- rd+ re- re+ 100twist pair cable or pcb trace 0.1uf 0.01uf 0.1uf 0.01uf lvdd lgnd pvdd pgnd f.bead BU8255KVT vdd gnd 0.1uf 0.01uf v dd clkout r4 r5 r6 r7 r8 r9 g4 g5 g6 g7 g8 g9 b4 b5 b6 b7 b8 b9 hsync vsync de r2 r3 g2 g3 b2 b3 r0 r1 g0 g1 b0 b1 pd clkout ra0 ra1 ra2 ra3 ra4 ra5 ra6 rb0 rb1 rb2 rb3 rb4 rb5 rb6 rc0 rc1 rc2 rc3 rc4 rc5 rc6 rd0 rd1 rd2 rd3 rd4 rd5 rd6 re0 re1 re2 re3 re4 re5 re6 dk r/f open open pd oe oe *3 *3
catalog no.08t238a '08.6 rohm ? when you order , please order in times the amount of package quantity. containe r quantit y direction of feed tray(with dry pack) 1000pcs direction of product is fixed in a tray. 1pin 1pin unit:mm) unit:mm) t q fp64v 0.1 33 48 16 1 12.0 0.3 10.0 0.2 0.125 0.1 0.5 0.2 0.1 0.1 0.1 1.0 0.1 0.5 49 64 32 17 10.0 0.2 12.0 0.3 t q fp64v

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